A charge pump is an electronic circuit that uses a pumping technique to generate a pump output voltage outside the range of supply voltages from which the pump operates. When the pump output voltage is greater than the upper limit of the power-supply range, the pump is commonly referred to as a positive charge pump. A charge pump whose output voltage is less than the lower limit of the power-supply range is commonly referred to as a negative charge pump. A charge pump typically contains a group of pump stages arranged in series. Each stage provides an incremental voltage increase or decrease, generally referred to as the stage voltage gain, in the pump output voltage.
FIG. 1 illustrates a conventional n-stage positive diode charge pump whose power-supply range is from ground reference (0 V) to a high voltage denoted here as VDD. The diode pump of FIG. 1 contains n substantially identical pn diodes D1-Dn, n respectively corresponding pump capacitors C1-Cn, output pn diode Dn+1, and output capacitor CO arranged as shown. Each pump stage consists of a diode Di and corresponding capacitor Ci where i is an integer varying from 1 to n. High supply voltage VDD is provided as an input signal to the D1 anode. Using output capacitor CO to reduce output voltage ripple, the Dn+1 cathode furnishes pump output voltage signal VPP at a relatively constant value greater than VDD.
Clock voltage VCK is provided to odd-numbered pump capacitors C1, C3, and so on. Even-numbered pump capacitors C2, C4, and so on receive clock voltage VCK inverse to clock voltage VCK. Voltages VCK and VCK vary between 0 and VDD at a suitable frequency as generally indicated in FIG. 2. The stage voltage gain is the same for each stage Di/Ci and can be as high as VDD−Vpn where Vpn denotes the voltage at which each diode Di starts to conduct current. Since each stage Di/Ci has the same stage voltage gain, output voltage VPP increases linearly with the number n of stages.
The diode pump of FIG. 1 is a highly efficient device. However, diode turn-on voltage Vpn is basically not scalable. As a result, the diode pump cannot be readily scaled downward as the power-supply voltage range is reduced in the course of decreasing the average integrated-circuit feature size. Also, providing an integrated circuit with pn diodes for a diode pump presents substantial fabrication difficulties.
The scaling and fabrication difficulties are overcome with the n-stage positive charge pump initially described in Dickson, “On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique,” IEEE J. Solid-State Circs., vol. SC-11, March 1976, pp. 374-378. FIG. 3 depicts the Dickson charge pump in which each diode Di of the diode pump of FIG. 1 is replaced with a diode-configured n-channel insulated-gate field-effect transistor (“FET”) Qi whose drain and gate electrode are connected together. The body regions of FETs Q1-Qn+1 are all grounded.
The stage voltage gain for the ith stage of the Dickson pump can be as high as VDD−VTi where VTi is the Qi threshold voltage. The high (or low) voltage at the source of each FET Qi increases as that FET Qi is further down the charge pump, i.e., as i increases. Because the body regions of FETs Q1-Qn are all grounded and thus at the same electrical potential, FETs Qi-Qn experience a body effect which causes threshold voltage VTi to increase as i increases. The stage voltage gain thereby decreases with increasing i. For the same number of stages and same voltage conditions at the first stage, the Dickson pump is less efficient than the diode pump.
Shin et al. (“Shin”), “A New Charge Pump Without Degradation in Threshold Voltage Due to Body Effect,” IEEE J. Solid-State Circs., vol. 35, August 2000, pp. 1227-1230, addresses the efficiency loss of the Dickson pump with the n-stage positive charge pump shown in FIG. 4. Shin replaces each FET Qi of the Dickson pump with a three-FET charge-transfer cell 20i consisting of p-channel charge-transfer FET QTi, p-channel source-side FET QSi, and p-channel drain-side FET QDi arranged as shown where i here varies from 1 to n+1. Each cell 20i provides cell output voltage signal VDi at the interconnected gate electrode and drain of that cell's charge-transfer FET QTi. Pump output voltage VPP is output voltage VDn+1 of output cell 20n+1. The body region of charge-transfer FET QTi in each cell 20i is connected to the interconnected drains of side FETs QSi and QDi to receive body voltage signal VBi.
Consider a cell 20i whose pump capacitor Ci receives clock voltage VCK. When voltage VCK goes low, charge-transfer FET QTi in that cell 20i turns on as cell output voltage VDi rapidly drops by an amount approximately equal to VDD. Charge passes through FET QTi to gradually raise voltage VDi by an amount less than VDD. FET QTi turns off when clock voltage VCK subsequently goes high. Voltage VDi rapidly increases by an amount approximately equal to VDD. Since clock voltage VCK goes low when voltage VCK goes high, charge-transfer FET QTi+1 in next cell 20i+1 turns on. Charge passes through FET QTi+1 to gradually reduce voltage VDi by an amount less than VDD. When Shins's charge pump is in steady-state operation, cell output voltage VDi thereby returns to approximately the value existing when clock voltage VCK went low. However, voltage VDi is of an average value greater than that of input voltage VDi-1 to cell 20i. The stage containing cell 20i thus has a voltage gain.
Subject to bipolar-action difficulties which arise with first cell 201 and output cell 20n+1 and which are discussed below in connection with FIGS. 6a and 6b, side FETs QS1-QSn+1 and QD1-QDn+1 operate generally in the following manner. When charge-transfer FET QTi in foregoing cell 20i turns on due to clock voltage VCK going low, source-side FET QSi turns on as drain-side FET QDi turns off. The body region of charge-transfer FET QTi is temporarily electrically connected to its source by way of an electrical path through source-side FET QSi. The reverse occurs when clock voltage VCK goes high to turn charge-transfer FET QTi off. Drain-side FET QDi turns on as source-side FET QSi turns off. The body region of charge-transfer FET QTi is then temporarily electrically connected to its drain by way of an electrical path through drain-side FET QDi so as to prevent body voltage VBi from electrically floating.
Importantly and again subject to the below-described bipolar-action difficulties, the temporary electrical connections of the body regions of charge-transfer FETs QT1-QTn+1 respectively to their sources when each FET QTi is in its conductive condition enables FETs QT1-QTn+1 to all effectively have the same zero back-bias threshold voltage VT0. Shin's pump largely avoids the body-effect threshold voltage increase, and the consequent stage voltage gain decrease, that arises with Dickson's pump as i increases. Shin presents a graph, substantially repeated in FIG. 5, which shows that Shin's pump is much more efficient than Dickson's pump and closely approaches the efficiency of the diode pump.
FIG. 6a cross-sectionally illustrates Shin's cell structure as applied to first cell 201. P-type semiconductor substrate 22 is provided with n-well 24 having four p+ regions of which p+ region 26 serves commonly as the QT1 drain and the QD1 source. P+ region 28 is the QD1 drain and is electrically connected to n-well 24 by way of n+ contact region 30. P-substrate 22, n-well 24, and p+ region 26 respectively constitute the collector, base, and emitter of parasitic pnp bipolar transistor 32 having parasitic collector resistance 34 and parasitic base resistance 36.
Pnp transistor 32 needs to be turned off for first cell 201 to operate properly. For transistor 32 to be turned off, cell output voltage VD1 at emitter 26 needs to be less than a VBE, typically 0.6-0.9 V, above body voltage VB1 at base 24. When clock voltage VCK goes high, voltage VD1 rapidly rises sufficiently above VDD that charge-transfer FET QT1 and source-side FET QS1 turn off. Drain-side FET QD1 is intended to turn on (strongly) and electrically connect its source 26 to n-well 24 by way of an electrical path through the QD1 channel region, QD1 drain 28, and contact region 30. When clock voltage VCK is high, body voltage VB1 is thus intended to substantially equal cell output voltage VD1 so that transistor 32 is turned off.
Fixed high supply voltage VDD applied to QD1 gate electrode 38 may, however, sometimes not be sufficiently less than cell output voltage VD1 during an entire VCK high interval, especially since voltage VD1 drops during the interval, for drain-side FET QD1 to be turned on strongly enough to ensure that body voltage VB1 is sufficiently close to voltage VD1 that pnp transistor 32 is turned off during the entire VCK high interval. Depending on various factors such as noise, manufacturing variations, and so on, body voltage VB1 may occasionally float sufficiently low that pnp transistor 32 turns on and conducts current to substrate 22. This bipolar action reduces the stage voltage gain of first cell 201. The stage voltage gain of later cells is also reduced so that the overall performance of Shin's pump is substantially degraded.
A similar, but complementary, bipolar-action phenomenon occurs in output cell 20n+1. Referring to FIG. 6b for a cross-sectional illustration of Shin's cell structure as applied to cell 20n+1, p-substrate 22 is further provided with n-well 40 having four p+ regions of which p+ region 42 serves as both the QTn+1 source and the QSn+1 source. P+ region 44 is the QSn+1 drain and is electrically connected to n-well 40 by way of n+ contact region 46. P-substrate 22, n-well 40, and p+ region 42 respectively constitute the collector, base, and emitter of parasitic pnp bipolar transistor 48 having parasitic collector resistance 50 and parasitic base resistance 52.
FIG. 6b illustrates the case in which n is an even number so that pump capacitor Cn receives clock voltage VCK. For pnp transistor 48 to be turned off as is necessary for output cell 20n+1 to operate properly, cell input voltage VDn at emitter 42 must be less than a VBE above body voltage VBn+1 at base 40. When clock voltage VCK goes high, voltage VDn applied to QDn+1 gate electrode 54 and QTn+1 source 42 rapidly rises sufficiently above pump output voltage VPP at the QDn+1 source and QTn+1 gate electrode 56 that drain-side FET QDn+1 turns off and charge-transfer FET QTn+1 simultaneously turns on. With region 42 also being the source of source-side FET QSn+1 and with its gate electrode 58 also receiving voltage VDn, FET QS1 is intended to likewise turn on (strongly) and electrically connect its source 42 to n-well 40 by way of an electrical path through the QS1 channel, QS1 drain 44, and contact region 46. When clock voltage VCK is high, body voltage VBn+1 is thus intended to substantially equal cell input voltage VDn so that transistor 48 is turned off.
Largely constant pump output voltage VPP applied to QSn+1 gate electrode 58 may, however, sometimes not be sufficiently less than input voltage VDn to output cell 20n+1 during an entire VCK high interval, especially since voltage VDn drops during the interval, for source-side FET QSn+1 to be turned on strong enough to ensure that body voltage VBn+1 is sufficiently close to voltage VDn that parasitic pnp transistor 48 is turned off during the entire VCK high interval. Again depending on factors such as noise, manufacturing variations, and so on, body voltage VBn+1 may occasionally float sufficiently low that pnp transistor 48 turns on and conducts current to substrate 22. Shin's pump can lose much of its voltage gain dependent on how long and how strongly transistor 48 is turned on.
The efficiency of Shin's pump is potentially very high. It would be desirable to have a charge pump that operates similarly to Shin's pump but avoids the bipolar-action difficulties that handicap its performance.